A 3.8-ns CMOS 16*16-b multiplier using complementary pass-transistor logic
- 1 April 1990
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 25 (2), 388-395
- https://doi.org/10.1109/4.52161
Abstract
No abstract availableThis publication has 6 references indexed in Scilit:
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