A reconfigurable WSI neural network
- 7 January 2003
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 141-150
- https://doi.org/10.1109/wafer.1989.47545
Abstract
The solution presented consists of implementing the N neuron Hopfield network as a systolic square array made up of N/sup 2/ cells. Systolic arrays are well suited to wafer-scale integration (WSI). Inherent error tolerance of neural networks facilitates wafer design. However, a wafer-level reconfiguration is required to bypass faulty chips. The principle and the architecture of a switching element which provides a flexible wafer-level reconfiguration is described.Keywords
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