Test generation for highly sequential circuits

Abstract

The authors address the problem of generating test sequences for stuck-at faults in nonscan synchronous sequential circuits. They present a novel test procedure that exploits both the structure of the combinational logic in the circuit as well as the sequential behavior of the circuit. In contrast to previous approaches, the authors decompose the problem of sequential test generation into three subproblems of combinational test generation, fault-free state justification, and fault-free state differentiation. They describe fast algorithms for state justification and state differentiation using the ON sets and OFF sets of flip-flop inputs and primary outputs. The decomposition of the testing problem into three subproblems rather than the traditional two, performing the justification and differentiation steps on the fault-free rather than the faulty machine, and the use of efficient techniques for cube intersection result in significant performance improvements over previous approaches.