Structure of the stepped Si/SiO2 interface after thermal oxidation: Investigations with scanning tunneling microscopy and spot-profile analysis of low-energy electron diffraction

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Abstract
After wet chemical oxide removal and fast transfer into ultrahigh vacuum the Si(111)/SiO2 interface structure of wafers from semiconductor‐industrial processes (polishing, oxidation, annealing) is investigated with scanning tunneling microscopy (STM): Regular terrace arrays with atomic step height are visible with STM after technological ex situ preparation. The local step structure varies, kinks at step edges occur, and irregular islands are formed with increasing oxide thickness and oxidation rate. The local STM information is compared to macroscopically averaged results provided by electron diffraction (spot‐profile analysis of low‐energy electron diffraction).