A novel CMOS analog neural oscillator cell
- 13 January 2003
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- Vol. 52, 794-797
- https://doi.org/10.1109/iscas.1989.100470
Abstract
A very flexible programmable CMOS analog neural oscillator cell architecture is presented. The proposed neuron circuit architecture is a hysteretic neural-type pulse oscillator. Its implementation consists of a transconductance comparator, a capacitor, and two nonlinear resistors. It has over nine decades of oscillation frequency range, i.e., from 10/sup -2/ Hz to 20 MHz. This range has been experimentally verified. The oscillator cell in the test chip was implemented in a standard 3- mu m (p-well), double-metal CMOS technology and has a dimension of about 44000 mu m/sup 2/ (without the capacitor). Preliminary measurements and simulated results agree very well.<>Keywords
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