A theory of reduced and minimal procedural dependencies
- 1 June 1991
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computers
- Vol. 40 (6), 681-692
- https://doi.org/10.1109/12.90247
Abstract
No abstract availableThis publication has 18 references indexed in Scilit:
- Modelling The Effects Of Instruction Queue Loading On A Static Instruction Stream Micro-architecturePublished by Institute of Electrical and Electronics Engineers (IEEE) ,2005
- SIMP (single Instruction Stream/multiple Instruction Pipelining): A Novel High-speed Single-processor ArchitecturePublished by Institute of Electrical and Electronics Engineers (IEEE) ,2005
- Concurrency extraction via hardware methods executing the static instruction streamIEEE Transactions on Computers, 1992
- HPSm, a high performance restricted data flow architecture having minimal functionalityACM SIGARCH Computer Architecture News, 1986
- HPS, a new microarchitecture: rationale and introductionPublished by Association for Computing Machinery (ACM) ,1985
- Fast Execution of Loops with IF StatementsIEEE Transactions on Computers, 1984
- Branch Prediction Strategies and Branch Target Buffer DesignComputer, 1984
- Representation of Concurrency with Ordering MatricesIEEE Transactions on Computers, 1973
- The Inhibition of Potential Parallelism by Conditional JumpsIEEE Transactions on Computers, 1972
- On the Number of Operations Simultaneously Executable in Fortran-Like Programs and Their Resulting SpeedupIEEE Transactions on Computers, 1972