Anomalous C-V characteristics of implanted poly MOS structure in n/sup +//p/sup +/ dual-gate CMOS technology
- 1 May 1989
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Electron Device Letters
- Vol. 10 (5), 192-194
- https://doi.org/10.1109/55.31717
Abstract
The C-V characteristics of arsenic-doped polysilicon show a gate-bias dependence of the inversion capacitance and a reduction in the expected value of the inversion capacitance. The characteristics have been investigated with quasistatic and high-frequency C-V as well as conductance measurements of various capacitors that have been subjected to annealing times and temperatures ranging from 900 degrees C/30 min to rapid thermal annealing at 1050 degrees C. The results can be explained by assuming that there is a depletion region forming in the polysilicon due to insufficient activation of the dopant at the polysilicon/oxide surface. The impact of this condition on the device characteristics is shown to be a 20-30% reduction in the G/sub m/ of NMOS transistors with 125-AA Gate oxide thickness.Keywords
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