Characterization of Lattice Defect Structures at GaAs/Si Interface by Transmission Electron Microscopy

Abstract

Lattice defect structure at GaAs/Si interface has been studied by transmission electron microscopy. The GaAs layer was grown by the two-step MOCVD growth procedure in which a thin GaAs buffer layer was grown at a low temperature(\lesssim450°C). The large misfit stress is found to be relieved by misfit dislocations at the GaAs/Si interface. These misfit dislocations are introduced during solid phase epitaxial regrowth of the polycrystalline buffer layer. The observed moire fringes for the buffer layer/Si system demonstrate that the lattice of the regrown buffer layer is relaxed to a nearly unstressed state, and thus, GaAs can be grown at higher temperatures (∼750°C) without generation of lattice defects.