High-speed bipolar logic circuits with low power consumption for LSI-a comparison
- 1 August 1982
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 17 (4), 703-712
- https://doi.org/10.1109/jssc.1982.1051800
Abstract
No abstract availableKeywords
This publication has 15 references indexed in Scilit:
- A simple optimisation procedure for bipolar subnanosecond ICs with low power dissipationMicroelectronics Journal, 1982
- Subnanosecond Self-Aligned I/sup 2/L/MTL CircuitsIEEE Journal of Solid-State Circuits, 1980
- Integrierte BipolarschaltungenPublished by Springer Nature ,1980
- A 1500 gate, random logic, large-scale integrated (LSI) mastersliceIEEE Journal of Solid-State Circuits, 1979
- STL TechnologyPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1979
- A 100 PS bipolar logicPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1977
- Control of Schottky barrier height using highly doped surface layersSolid-State Electronics, 1976
- Applications of low-level differential logicPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1975
- Terminal-oriented model for merged transistor logic (MTL)IEEE Journal of Solid-State Circuits, 1974
- Reducing the effective height of a Schottky barrier using low-energy ion implantationApplied Physics Letters, 1974