Morphology and electronic transport of polycrystalline pentacene thin-film transistors

Abstract

Temperature-dependent measurements of thin-film transistors were performed to gain insight in the electronic transport of polycrystalline pentacene. Devices were fabricated with plasma-enhanced chemical vapor deposited silicon nitride gate dielectrics. The influence of the dielectric roughness and the deposition temperature of the thermally evaporated pentacene films were studied. Although films on rougher gate dielectrics and films prepared at low deposition temperatures exhibit similar grain size, the electronic properties are different. Increasing the dielectric roughness reduces the free carrier mobility, while low substrate temperature leads to more and deeper hole traps.