Clustering based simulated annealing for standard cell placement

Abstract

The authors present a novel technique for reducing the effective problem size for simulated annealing without compromising the solution quality. They form clusters of cells based on their interconnections, and place them first using conventional simulated annealing. They then break up the clusters, and place the individual cells using another simulated annealing process that does a refinement on the placement. The original problem is thus divided into two subproblems, each requiring much less time. The results of this two-stage simulated annealing have been superior to those with a conventional simulated annealing implementation, with more significant improvements observed for larger chips. For chips with more than 2500 cells, the authors report a factor-of-two-to-three speed-up in CPU time, together with a 6-to-17% improvement in the estimated wire length.