A room temperature 0.1 μm CMOS on SOI
- 1 January 1994
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Electron Devices
- Vol. 41 (12), 2405-2412
- https://doi.org/10.1109/16.337456
Abstract
No abstract availableKeywords
This publication has 14 references indexed in Scilit:
- Thin-film SOI technology: the solution to many submicron CMOS problemsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- High-performance CMOS fabricated on ultrathin BESOI with sub-10 nm ttvPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Measurement of SOI MOSFET I-V characteristics without self-heatingPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Optimization of two-dimensional collector doping profiles for submicron BiCMOS technologiesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- High-performance devices for a 0.15- mu m CMOS technologyIEEE Electron Device Letters, 1993
- Indium channel implant for improved short-channel behavior of submicrometer NMOSFETsIEEE Electron Device Letters, 1993
- Anomalous voltage overshoot during turn-off of thin-film n-channel SOI MOSFETsIEEE Electron Device Letters, 1993
- A 2-ns cycle, 3.8-ns access 512-kb CMOS ECL SRAM with a fully pipelined architectureIEEE Journal of Solid-State Circuits, 1991
- Reduction of kink effect in thin-film SOI MOSFETsIEEE Electron Device Letters, 1988
- Finite-Element Analysis of Semiconductor Devices: The FIELDAY ProgramIBM Journal of Research and Development, 1981