A substrate-plate trench-capacitor (SPT) memory cell for dynamic RAM's
- 1 October 1986
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 21 (5), 627-634
- https://doi.org/10.1109/jssc.1986.1052587
Abstract
No abstract availableThis publication has 13 references indexed in Scilit:
- Plate-noise analysis of an on-chip generated half-VDD biased-plate PMOS cell in CMOS DRAMsIEEE Journal of Solid-State Circuits, 1985
- A self-aligned 1-µm-channel CMOS technology with retrograde n-well and thin epitaxyIEEE Transactions on Electron Devices, 1985
- A trench transistor cross-point DRAM cellPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1985
- Submicron CMOS technologies for four mega bit dynamic RAMPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1985
- Fundamental limitations on DRAM storage capacitorsIEEE Circuits and Devices Magazine, 1985
- Accuracy of an effective channel length/External resistance extraction algorithm for MOSFET'sIEEE Transactions on Electron Devices, 1984
- Half-V/SUB DD/ bit-line sensing scheme in CMOS DRAMsIEEE Journal of Solid-State Circuits, 1984
- An experimental 1Mb DRAM with on-chip voltage limiterPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1984
- Depletion trench capacitor technology for megabit level MOS dRAMIEEE Electron Device Letters, 1983