Yield and reliability of MNOS EEPROM products
- 1 January 1989
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 24 (6), 1714-1722
- https://doi.org/10.1109/4.45010
Abstract
No abstract availableThis publication has 11 references indexed in Scilit:
- High-resolution transmission electron microscopy study of 1.5 nm ultrathin tunnel oxides of metal-nitride-oxide-silicon nonvolatile memory devicesApplied Physics Letters, 1988
- Improvement of Written-State Retentivity by Scaling Down MNOS Memory DevicesJapanese Journal of Applied Physics, 1988
- Endurance of EEPROMs with On-Chip Error CorrectionIEEE Transactions on Reliability, 1987
- A temperature- and process-tolerant 64K EEPROMIEEE Journal of Solid-State Circuits, 1985
- Hi-MNOS II Technology for a 64-kbit Byte-Erasable 5-V-Only EEPROMIEEE Journal of Solid-State Circuits, 1985
- A 256K high performance CMOS EEPROM technologyPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1985
- Endurance model for textured-poly floating gate memoriesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1984
- High-voltage regulation and process considerations for high-density 5 V-only E/sup 2/PROM'sIEEE Journal of Solid-State Circuits, 1983
- Scaling Down MNOS Nonvolatile Memory DevicesJapanese Journal of Applied Physics, 1982
- Computation of integrated-circuit yields from the distribution of slice yields for the individual devicesIEEE Transactions on Electron Devices, 1968