Circuit techniques in a 266-MHz MMX-enabled processor
- 1 January 1997
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 32 (11), 1650-1664
- https://doi.org/10.1109/4.641685
Abstract
No abstract availableKeywords
This publication has 12 references indexed in Scilit:
- A 160 MHz 32 b 0.5 W CMOS RISC microprocessorPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Flow-through latch and edge-triggered flip-flop hybrid elementsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A 300 MHz CMOS microprocessor with multi-media technologyPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A 300 MHz 64 b quad-issue CMOS RISC microprocessorPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A 64-b microprocessor with multimedia supportIEEE Journal of Solid-State Circuits, 1995
- 6 ns cycle 256 kb cache memory and memory management unitPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1993
- A PLL clock generator with 5 to 110 MHz of lock range for microprocessorsIEEE Journal of Solid-State Circuits, 1992
- A 2ns Cycle, 4ns Access 512kb CMOS ECL SRAMPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1991
- A 30-MHz hybrid analog/digital clock recovery circuit in 2- mu m CMOSIEEE Journal of Solid-State Circuits, 1990
- A variable delay line PLL for CPU-coprocessor synchronizationIEEE Journal of Solid-State Circuits, 1988