The NAPA adaptive processing architecture
- 27 November 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
No abstract availableThis publication has 8 references indexed in Scilit:
- Field programmable gate array based reconfigurable preprocessorPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- NAPA C: compiling for a hybrid RISC/FPGA architecturePublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Garp: a MIPS processor with a reconfigurable coprocessorPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Teramac-configurable custom computingPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Baring it all to software: Raw machinesComputer, 1997
- OneChip: an FPGA processor with reconfigurable logicPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1996
- On a Class of Multistage Interconnection NetworksIEEE Transactions on Computers, 1980
- Data Manipulating Functions in Parallel Processors and Their ImplementationsIEEE Transactions on Computers, 1974