Increasing the noise margin in organic circuits using dual gate field-effect transistors
- 7 April 2008
- journal article
- Published by AIP Publishing in Applied Physics Letters
- Vol. 92 (14)
- https://doi.org/10.1063/1.2904624
Abstract
Complex digital circuits reliably work when the noise margin of the logic gates is sufficiently high. For p-type only inverters, the noise margin is typically about 1V. To increase the noise margin, we fabricated inverters with dual gate transistors. The top gate is advantageously used to independently tune the threshold voltage. The shift can be quantitatively described by ΔVth=(Ct∕Cb)Vtopgate, where Ct and Cb are the top and bottom gate capacitances. We show that by adjusting the top gate biases, the noise margin of dual gate inverters can be significantly improved up to about 5V.Keywords
This publication has 10 references indexed in Scilit:
- Reduction in operation voltage of complementary organic thin-film transistor inverter circuits using double-gate structuresApplied Physics Letters, 2007
- A 13.56-MHz RFID System Based on Organic TranspondersIEEE Journal of Solid-State Circuits, 2006
- Influence of transistor parameters on the noise margin of organic digital circuitsIEEE Transactions on Electron Devices, 2006
- Organic double-gate field-effect transistors: Logic-AND operationApplied Physics Letters, 2005
- Double-gate organic field-effect transistorApplied Physics Letters, 2005
- Dual-gate organic thin-film transistorsApplied Physics Letters, 2005
- Control of threshold voltage of organic field-effect transistors with double-gate structuresApplied Physics Letters, 2005
- Flexible active-matrix displays and shift registers based on solution-processed organic transistorsNature Materials, 2004
- Dopant density determination in disordered organic field-effect transistorsJournal of Applied Physics, 2003
- Noise margin criteria for digital logic circuitsIEEE Transactions on Education, 1993