Parallel global routing for standard cells
- 1 January 1990
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
- Vol. 9 (10), 1085-1095
- https://doi.org/10.1109/43.62733
Abstract
The potential speedup of a standard cell global router using a general-purpose multiprocessor is investigated. LocusRoute, a global routing algorithm for standard cells, and its parallel implementation are presented. The uniprocessor speed and quality of LocusRoute is comparable to modern global routers. LocusRoute compares favorably with the TimberWolf 5.0 global router and a maze router that searches the same space more completely. Two successful methods of parallel decomposition of the router are presented. The first, in which multiple wires are routed in parallel, uses the notion of chaotic parallelism to achieve significant performance gains by relaxing data dependencies, at the cost of a minor loss in quality. Using iteration and careful assignment of wires to processors, this degradation is reduced. The approach achieves measured speedups from 5 to 14 using 15 processors. The second parallel decomposition technique is the evaluation of different routes for each wire on separate processors. It achieves speedups of up to 6 using 10 processors. It is demonstrated that when these two approaches are combined, the aggregate speedup is the product of the individual approaches' speedup, and, using an improved scheduling approach, it can be even greater. With a simple model based on these results, speedups of more than 75 using 150 processors are predictedKeywords
This publication has 22 references indexed in Scilit:
- A new algorithm for standard cell global routingIntegration, 1992
- A quadrisection-based combined place and route scheme for standard cellsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1989
- ThunderBird: a complete standard cell layout packageIEEE Journal of Solid-State Circuits, 1988
- A hardware accelerator for maze routingPublished by Association for Computing Machinery (ACM) ,1987
- A Class of Array Architectures for Hardware Grid RoutersIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1986
- The TimberWolf placement and routing packageIEEE Journal of Solid-State Circuits, 1985
- A Class of Cellular Architectures to Support Physical Design AutomationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1984
- Reducing Channel Density in Standard Cell LayoutPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1983
- An Algorithm for Path Connections and Its ApplicationsIEEE Transactions on Electronic Computers, 1961
- On the Shortest Spanning Subtree of a Graph and the Traveling Salesman ProblemProceedings of the American Mathematical Society, 1956