The ITFET: A Novel FinFET-Based Hybrid Device
- 21 August 2006
- journal article
- research article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Electron Devices
- Vol. 53 (9), 2335-2343
- https://doi.org/10.1109/ted.2006.880813
Abstract
A novel nanoscale hybrid device (the ITFET) comprising a double-gate (DG) FinFET and a single-gate silicon-on-insulator (SOI) MOSFET, with a common gate, is defined and assessed using a process/physics-based compact model [University of Florida DG model (UFDG)] and 3-D numerical simulations. Significantly higher, and variable, on-state current per pitch, relative to the current of the FinFET, can be achieved with a properly designed ITFET, with the off-state current being governed by the body thickness of the (fully depleted) SOI device. The ITFET can be especially advantageous in FinFET circuits that require device ratioing, such as the 6T-static random access memory (SRAM) cell. Outstanding UFDG/Spice3-predicted characteristics of the FinFET-based SRAM cell, with ITFETs used for the pull-down transistors without any area penalty, are presentedKeywords
This publication has 11 references indexed in Scilit:
- Bulk Inversion in FinFETs and Implied Insights on Effective Gate WidthIEEE Transactions on Electron Devices, 2005
- Quantum-mechanical effects on the threshold voltage of undoped double-gate MOSFETsIEEE Electron Device Letters, 2005
- On the Feasibility of Nanoscale Triple-Gate CMOS TransistorsIEEE Transactions on Electron Devices, 2005
- Nanoscale FinFETs with gate-source/drain underlapIEEE Transactions on Electron Devices, 2004
- Scaling fully depleted SOI CMOSIEEE Transactions on Electron Devices, 2003
- Sub 50-nm FinFET: PMOSPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Speed superiority of scaled double-gate CMOSIEEE Transactions on Electron Devices, 2002
- Analytical modeling of quantization and volume inversion in thin Si-film DG MOSFETsIEEE Transactions on Electron Devices, 2002
- Double-gate CMOS: symmetrical- versus asymmetrical-gate devicesIEEE Transactions on Electron Devices, 2001
- Static-noise margin analysis of MOS SRAM cellsIEEE Journal of Solid-State Circuits, 1987