The ITFET: A Novel FinFET-Based Hybrid Device

Abstract

A novel nanoscale hybrid device (the ITFET) comprising a double-gate (DG) FinFET and a single-gate silicon-on-insulator (SOI) MOSFET, with a common gate, is defined and assessed using a process/physics-based compact model [University of Florida DG model (UFDG)] and 3-D numerical simulations. Significantly higher, and variable, on-state current per pitch, relative to the current of the FinFET, can be achieved with a properly designed ITFET, with the off-state current being governed by the body thickness of the (fully depleted) SOI device. The ITFET can be especially advantageous in FinFET circuits that require device ratioing, such as the 6T-static random access memory (SRAM) cell. Outstanding UFDG/Spice3-predicted characteristics of the FinFET-based SRAM cell, with ITFETs used for the pull-down transistors without any area penalty, are presented