Electron Beam Direct Writing Technology for 64-Mb DRAM LSIs

Abstract

This paper describes the electron beam direct writing technology for 64-Mb DRAM LSIs including a resist process for 0.3-µm resolution, the prevention of the charging problem by a conducting polymer, and proximity effect correction by both the pattern classification method and the subsidiary exposure method. A large amount of pattern data is processed after dividing the whole chip data into peripheral circuits and 256-kb memory mats. An experimental 64-Mb DRAM LSI is fabricated by these technologies.