Solid-State Delay of Analog Signals
- 1 June 1968
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 3 (2), 179-181
- https://doi.org/10.1109/JSSC.1968.1049866
Abstract
A solid-state system for the delay of analog signals that lends itself to integrated circuit fabrication is described. The system utilizes the FM record-reproduce electronics of a tape recorder for the delay of recorded or "on line" signals. A monostable multivibrator delay chain of any length is inserted in the reproduce electronics for incremental or continuous changes in delay. The delay of analog signals is illustrated with a 47-stage delay chain providing a 235- /spl mu/ s delay of signals recorded at 60 in/s on a standard bandwidth IRIG FM tape recorder. This same delay chain will provide a 7.52ms delay at 1 7/8 in/s by changing the plug-in timing capacitors.Keywords
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