Dislocation propagation and emitter edge defects in silicon wafers

Abstract

Some transistor defects show a tendency to occur near the edges of emitters. Like ’’area defects’’, these ’’edge defects’’ occur in silicon wafers in a distribution pattern reminiscent of thermal‐stress‐induced dislocations. A peculiar feature is that often a number of edge defects which are close replicas of one another occur in a string, each in one of the neighboring emitters. Such edge defects are preponderant in transistors having silicon nitride surface films. In our proposed model, these emitter edge defects are generated when thermal‐stress‐induced dislocations glide through a row of emitters and interact with the emitter edge stresses, thereby, and under appropriate conditions, casting off small dislocation half‐loops which straddle the edges. The model is shown to be consistent with all the observed phenomena pertaining to the emitter edge defect. To provide a foundation for the discussion of the finer details of the emitter edge defects, we also present an analysis of the nature and distribution of thermally induced dislocations, itself a topic of general interest.