An ultra-low on-resistance power MOSFET fabricated by using a fully self-aligned process

Abstract

An ultra-low on-resistance power MOSFET fabricated by use of a fully self-aligned process is demonstrated. The feature of the new process is that most of the processing steps, such as channel formation, gate definition, and contact-hole opening, are carried out through a single masking step. This permits a remarkable increase in packing density, and thereby conducts the reduction of the channel resistance. A gate width per unit area of 50 cm /mm²has been implemented by using the new process with a 4-µm-pitch layout rule. This value is at least four times larger than that of the conventional VDMOSFET. The experimentally fabricated device, which possesses a total gate width of 480 cm in a 3.8 mm × 4.0 mm chip, exhibited an on-resistance of 9 mΩ and a breakdown voltage of 30 V. The resulting on-resistance area product of 137 mΩ .mm²is the smallest value ever reported.