Experimental Fabrication of XMOS Transistors Using Lateral Solid-Phase Epitaxy of CVD Silicon Films

Abstract

Experimental fabrication of an XMOS transistor which has two insulated gates called upper-gate and lower-gate has been performed using lateral solid-phase epitaxy of a-Si film deposited by CVD of SiH₄. The fabricated XMOS transistors exhibited no punch-through effect and good controllability of the upper-gate threshold voltage by the voltage applied to the lower-gate. It was found that the measured values of the slopes on the upper-gate threshold voltage control by the lower-gate voltage showed good agreement with the calculated value of the slope derived from a simple capacitance couple model.