A 90ns 4Mb DRAM in a 300 mil DIP
- 1 January 1987
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- Vol. XXX, 12-13
- https://doi.org/10.1109/isscc.1987.1157143
Abstract
A 4Mb DRAM employing a folded-bitline adaptive sidewall - isolated capacitance cell with 2μm deep trenches, a 72.3mm2chip size and 90ns access time will be described. Also incorporated are full bonding options for 4Mb×1 or 1Mb×4 organizations and for static column or page-mode operation.Keywords
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