Probabilistic construction and manipulation of Free Boolean Diagrams
- 30 December 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
No abstract availableKeywords
This publication has 10 references indexed in Scilit:
- Logic verification using binary decision diagrams in a logic synthesis environmentPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Sequential circuit design using synthesis and optimizationPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Dynamic variable ordering for ordered binary decision diagramsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Efficient implementation of a BDD packagePublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Comparing two-level and ordered binary decision diagram representations of logic functionsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1993
- Probabilistic verification of Boolean functionsFormal Methods in System Design, 1992
- On the complexity of VLSI implementations and graph representations of Boolean functions with application to integer multiplicationIEEE Transactions on Computers, 1991
- Graph-Based Algorithms for Boolean Function ManipulationIEEE Transactions on Computers, 1986
- Equivalence of free boolean graphs can be decided probabilistically in polynomial timeInformation Processing Letters, 1980
- The complexity of equivalence and containment for free single variable program schemesLecture Notes in Computer Science, 1978