Integrating adaptive on-chip storage structures for reduced dynamic power
- 26 June 2003
- proceedings article
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
No abstract availableThis publication has 13 references indexed in Scilit:
- Reducing set-associative cache energy via way-prediction and selective direct-mappingPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2005
- Reducing power requirements of instruction scheduling through dynamic allocation of multiple datapath resourcesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2005
- Drowsy caches: simple techniques for reducing leakage powerPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- The non-critical buffer: using load latency tolerance to improve data cache efficiencyPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- The Alpha 21264 microprocessor architecturePublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Static energy reduction techniques for microprocessor cachesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Cache decay: exploiting generational behavior to reduce cache leakage powerPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Energy-effective issue logicPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2001
- Design challenges of technology scalingIEEE Micro, 1999
- The 16-fold way: a microparallel taxonomyPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1993