Stacked high-ε gate dielectric for gigascale integration of metal–oxide–semiconductor technologies

Abstract

Advances in lithography and thinner ${\mathrm{SiO}}_{\mathrm{2}}$ gate oxides have enabled the scaling of metal–oxide–semiconductor technologies to sub-0.25 μm feature size. A major hurdle in the gate dielectric scaling using conventional thermally grown ${\mathrm{SiO}}_{\mathrm{2}}$ has been excessive tunneling that occurs in ultrathin $\text{(<25\hspace{0.17em}Å)}$ ${\mathrm{SiO}}_{\mathrm{2}}.$ High dielectric constant materials such as ${\mathrm{Ta}}_{\mathrm{2}}{\mathrm{O}}_{\mathrm{5}}$ have been suggested as a substitute for ${\mathrm{SiO}}_{\mathrm{2}}.$ However, these materials have high concentrations of bulk fixed charge, unacceptable levels of ${\mathrm{Si–Ta}}_{\mathrm{2}}{\mathrm{O}}_{\mathrm{5}}$ interface trap states, and low silicon interface carrier mobilities. This letter summerizes an elegant solution to these issues through synthesis of a thermally grown ${\mathrm{SiO}}_{\mathrm{2}}{\mathrm{(15\hspace{0.17em}\AA )–Ta}}_{\mathrm{2}}{\mathrm{O}}_{\mathrm{5}}{\mathrm{(30\hspace{0.17em}\AA )–SiO}}_{\mathrm{2}}\mathrm{(5–10\hspace{0.17em}\AA )}$ dielectric with improvements in leakage, tunneling, charge trapping behavior, and interface substructure. Transistors fabricated using this stacked gate dielectric exhibit excellent subthreshold, saturation, and drive currents.