GORDIAN: a new global optimization/rectangle dissection method for cell placement
- 6 January 2003
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
A placement method for cell-based layout styles composed of alternating and interacting global optimization and partitioning phases is presented. In contrast to other methods using the divide-and-conquer paradigm, it maintains the simultaneous treatment of all cells during optimization over all levels of partitioning. In the global optimization phases, constrained quadratic optimization problems with unique global minima are solved. Their solutions induce the assignment of cells to regions during the partitioning phases. For general-cell circuits, a highly efficient exhaustive slicing procedure is applied to small subsets of cells. The designer may choose a configuration from a menu to meet his requirements on chip area, chip aspect ratio and wire length. Placements with high area utilization are obtained within short computation times. The method has been applied to general-cell and standard-cell circuits with up to 3000 cells and nets.<>Keywords
This publication has 10 references indexed in Scilit:
- A new area and shape function estimation technique for VLSI layoutsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Mason: A Global Floorplanning Approach for VLSI DesignIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1986
- On the relative placement and the transportation problem for standard-cell layoutPublished by Association for Computing Machinery (ACM) ,1986
- A Procedure for Placement of Standard-Cell VLSI CircuitsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1985
- Near-optimal placement using a quadratic objective functionPublished by Association for Computing Machinery (ACM) ,1985
- Module Placement Based on Resistive Network OptimizationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1984
- A Linear-Time Heuristic for Improving Network PartitionsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1982
- A Combined Force and Cut Algorithm for Hierarchical VLSI LayoutPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1982
- A Min-Cut Placement Algorithm for General Cell Assemblies Based on a Graph RepresentationPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1979
- An Efficient Heuristic Procedure for Partitioning GraphsBell System Technical Journal, 1970