A 20-V four-quadrant CMOS analog multiplier
- 1 December 1985
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 20 (6), 1158-1168
- https://doi.org/10.1109/jssc.1985.1052454
Abstract
A novel technique is presented for performing the analog multiplication in CMOS technology. The circuit handles a wide range of input voltages. The MSO version of Gilbert's six-transistor cell (GSTC) is the basis for this multiplier. A simple source-coupled pair is used to study the MOS GSTC. Then, a technique is introduced for linearizing the source-coupled circuit. This scheme is extended to the MOS GSTC. The voltage ranges are further increased by introducing the folded CMOS GSTC.Keywords
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