An 0.1-μm voidless double-deck-shaped (DDS) gate HJFET with reduced gate-fringing-capacitance
- 1 May 1999
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Electron Devices
- Vol. 46 (5), 859-864
- https://doi.org/10.1109/16.760390
Abstract
No abstract availableKeywords
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