A programmable video signal processor
- 13 January 2003
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 2476-2479
- https://doi.org/10.1109/icassp.1989.266969
Abstract
A description is given of a digital, general-purpose, programmable processor chip, especially designed for effective processing of video signals. The architecture is described in terms of three hierarchical levels: the system level, describing how video signal processing tasks are realized on the basis of only one type of processor chip; the chip level, describing the modular architecture with the number of modules on the chip to be tuned to the available technology; and the module level, describing the various processing elements, how they communicate, and how they are controlled by so-called cyclo-static programs. For program development, software support tools have been designed, in a top-down mapping trajectory, that start at the signal-flow-graph level and result in the program code for the processor(s) Author(s) Sluyter, R.J. Philips Res. Lab., Eindhoven, Netherlands Snijder, P.J. ; Dijkstra, H. ; Huizer, C.M. ; van Roermund, A.H.M.Keywords
This publication has 6 references indexed in Scilit:
- The optimal synchronous cyclo-static array: A multiprocessor supercomputer for digital signal processingPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2005
- A programmable 1400 MOPS video signal processorPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1989
- A microprogrammable real-time video signal processor (VSP) LSIIEEE Journal of Solid-State Circuits, 1987
- Warp architecture and implementationACM SIGARCH Computer Architecture News, 1986
- Dubrovnik impasse puts high-definition TV on hold: A report on the turmoil in setting program standards concludes with a scenario for future developmentsIEEE Spectrum, 1986
- Block-shift invariance and block implementation of discrete-time filtersIEEE Transactions on Circuits and Systems, 1980