Optimal logic synthesis and testability: two faces of the same coin

Abstract

The relationships between test generation and logic minimization are described. An overview of the state of the art in combinational and sequential logic synthesis is provided. Combinational logic synthesis algorithms which can ensure irredundant and fully testable combinational circuits are reviewed. Test vectors which detect all single stuck-at faults in the combination logic can be obtained as a by-product of the logic minimization step. Equally intimate relationships between the problems of sequential logic synthesis and sequential test generation are envisioned. A recently developed synthesis technique of constrained state assignment and logic optimization which ensures fully testable sequential machines is described briefly.