Approximation of wiring delay in MOSFET LSI
- 1 August 1983
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 18 (4), 418-426
- https://doi.org/10.1109/jssc.1983.1051966
Abstract
Two approximation methods for wiring delay in MOS LSI are studied. One is analytical and the other is a lumped circuit approximation. The basic model for wiring is a distributed CR line with a drive MOSFET at one end and a capacitive load at the other end. Simple approximated formulas for the delay and the step response of this model are obtained. Approximation of a distributed CR line by lumped Rs and C's combination, which is very useful when incorporated in circuit simulation programs, is also investigated. The widely used L ladder circuit model is found to be a poor approximation, while /spl pi/ and T ladder circuit models give satisfactory results. The simplest circuits that approximate the interconnection line within a given tolerant error are tabulated under various drive and load conditions.Keywords
This publication has 7 references indexed in Scilit:
- Simple formulas for two- and three-dimensional capacitancesIEEE Transactions on Electron Devices, 1983
- Resistivities of Thin Film Transition Metal SilicidesJournal of the Electrochemical Society, 1982
- Signal Delay in RC Tree NetworksPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1981
- Refractory silicides for integrated circuitsJournal of Vacuum Science and Technology, 1980
- Modelling distributed RC lines for the transient analysis of complex networks†International Journal of Electronics, 1974
- Accurate metallization capacitances for integrated circuits and packagesIEEE Journal of Solid-State Circuits, 1973
- Time-Domain Analysis and Measurement Techniques for Distributed RC Structures. II. Impulse Measurement TechniquesJournal of Applied Physics, 1969