Low-temperature (<or=550 degrees C) fabrication of poly-Si thin-film transistors

Abstract

High performance n- and p-channel thin-film transistors (TFTs) have been fabricated in polycrystalline silicon films using a self-aligned-gate process without exceeding 550 degrees C. This process features the use of polycrystalline Si/sub 0.5/Ge/sub 0.5/ for the gate material and high-dose H/sup +/ implantation for grain-boundary passivation so that shorter process times can be used. Low threshold voltages of 2.8 and -0.2 V, and high field-effect mobilities of 35 and 28 cm/sup 2//V-s, where achieved by the NMOS and PMOS devices, respectively. The performance of these devices is comparable to that of previously reported devices fabricated using process temperatures up to 600 degrees C, and is adequate for large-area-display peripheral driver circuits. The significant reduction in maximum process temperature makes this process advantageous for the fabrication of CMOS circuits on large-area glass substrates.