The subthreshold behavior of SOS MOST's
- 1 August 1978
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Electron Devices
- Vol. 25 (8), 885-889
- https://doi.org/10.1109/t-ed.1978.19196
Abstract
MOST subthreshold behavior is of importance in many modern dynamic and very-low-power circuits. SOS MOST's exhibit quite generally a lower transconductance than bulk Si MOST's. Comparison between SOS and bulk Si MOST's is made on the basis of a simple model in the weak inversion region. Experiments with n-and p-channel SOS MOST's fabricated with epi Si layer thicknesses ranging from 0.1 to 3 µm confirm the predicted decrease of transconductance in weak inversion with decreasing thickness. Quantitative agreement between model and experience is obtained if a ∼350-Å thick nonconductive Si layer near the Si-sapphire interface is assumed. A transconductance jump observed for epi Si thickness equal to the surface maximum depletion width has not yet been explained. Further experiments including fabrication process, back-gate voltage measurements, and device dimensions were performed in order to investigate the low-transconductance origin. It is concluded that the only relevant parameters are the epi Si layer thickness and the high density of fast states at the Si-sapphire interface.Keywords
This publication has 8 references indexed in Scilit:
- CMOS analog integrated circuits based on weak inversion operationsIEEE Journal of Solid-State Circuits, 1977
- Very small MOSFET's for low-temperature operationIEEE Transactions on Electron Devices, 1977
- Interface properties of Si on sapphire and spinelJournal of Vacuum Science and Technology, 1976
- Theory of the MOS transistor in weak inversion-new method to determine the number of surface statesIEEE Transactions on Electron Devices, 1975
- An investigation of the silicon—Sapphire interface using the MIS capacitance methodIEEE Transactions on Electron Devices, 1975
- Ion-implanted complementary MOS transistors in low-voltage circuitsIEEE Journal of Solid-State Circuits, 1972
- High-performance low-power CMOS memories using silicon-on-sapphire technologyIEEE Journal of Solid-State Circuits, 1972
- Variations in Electrical Properties of Silicon Films on Sapphire Using the MOS Hall TechniqueApplied Physics Letters, 1972