Time-Interleaved and Circuit-Shared Dual-Channel 10 b 200 MS/s 0.18 $\mu{\rm m}$ CMOS Analog-to-Digital Convertor
- 19 February 2013
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Very Large Scale Integration (VLSI) Systems
- Vol. 21 (12), 2206-2213
- https://doi.org/10.1109/tvlsi.2012.2229305
Abstract
This paper proposes a 10 b 200 MS/s pipeline analog-to-digital convertor (ADC) for high-quality video systems based on double-channel and op-amp sharing schemes to minimize power consumption and channel mismatch. The double channel time-interleaved scheme reduces the required operating speed of amplifiers in the sample-and-hold amplifier and multiplying digital-to-analog (D/A) converters by 50%. The switched and shared op-amp with two input pairs amplifies each channel signal without extra series switches while minimizing the gain, bandwidth and offset mismatches between channels. The low-jitter sampling clock with a 50% duty cycle improves the dynamic performance of the wideband input signals significantly. The Flash ADCs employ a differential difference amplifier type pre-amp to continuously process dual-channel outputs. The prototype ADC in a 0.18 μm CMOS technology demonstrates the measured differential nonlinearity and integral nonlinearity within 0.62 and 0.99 LSB, respectively. At 200 MS/s, the ADC shows a maximum SNDR of 52.8 dB and a maximum SFDR of 60.4 dB. The ADC with an active die area of 1.28 mm2 consumes 54.0 mW at 1.8 V.Keywords
This publication has 14 references indexed in Scilit:
- Ten-bit 100 MS/s 24.2 mW 0.8 mm2 0.18 [micro sign]m CMOS pipeline ADC based on maximal circuit sharing schemesElectronics Letters, 2009
- A 0.31 pJ/Conversion-Step 12-Bit 100 MS/s 0.13 .MU.m CMOS A/D Converter for 3G Communication SystemsIEICE Transactions on Electronics, 2009
- Time-interleaved analog-to-digital convertersPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2008
- A 1.35 GS/s, 10 b, 175 mW Time-Interleaved AD Converter in 0.13 µm CMOSIEEE Journal of Solid-State Circuits, 2008
- Calibration-free 14b 70MS/s 0.13 [micro sign]m CMOS pipeline A/D converters based on high-matching 3D symmetric capacitorsElectronics Letters, 2007
- A 14-b linear capacitor self-trimming pipelined ADCIEEE Journal of Solid-State Circuits, 2004
- A digitally self-calibrating 14-bit 10-MHz CMOS pipelined A/D converterIEEE Journal of Solid-State Circuits, 2002
- A 10-bit 200-MS/s CMOS parallel pipeline A/D converterIEEE Journal of Solid-State Circuits, 2001
- A CMOS fully balanced differential difference amplifier and its applicationsIEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 2001
- A 250-mW, 8-b, 52-Msamples/s parallel-pipelined A/D converter with reduced number of amplifiersIEEE Journal of Solid-State Circuits, 1997