Feasibility of an ultra-high-speed Josephson multiplier
- 1 February 1987
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 22 (1), 98-103
- https://doi.org/10.1109/jssc.1987.1052677
Abstract
No abstract availableThis publication has 11 references indexed in Scilit:
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- Ultrahigh-speed logic gate family with Nb/Al-AlOx/Nb Josephson junctionsIEEE Transactions on Electron Devices, 1986
- Self-aligned contact process for Nb/Al-AlOx/Nb Josephson junctionsApplied Physics Letters, 1986
- A 280-ps Josephson 4-bitx4-bit parallel multiplierIEEE Journal of Solid-State Circuits, 1985
- High quality Nb/Al-AlOx/Nb Josephson junctionApplied Physics Letters, 1985
- 5.6 ps Gate Delay All Refractory Josephson OR Gate with Modified Variable Threshold LogicJapanese Journal of Applied Physics, 1985
- A 4.2-ps logic gate using new Pb-alloy Josephson IC technologyIEEE Electron Device Letters, 1985
- 9 ps Gate Delay Josephson OR Gate with Modified Variable Threshold LogicJapanese Journal of Applied Physics, 1985
- High quality refractory Josephson tunnel junctions utilizing thin aluminum layersApplied Physics Letters, 1983
- Generation and measurement of ultrashort current pulses with Josephson devicesApplied Physics Letters, 1980