A Two-Dimensional Etching Profile Simulator: ESPRIT
- 1 May 1987
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
- Vol. 6 (3), 417-422
- https://doi.org/10.1109/tcad.1987.1270287
Abstract
No abstract availableThis publication has 10 references indexed in Scilit:
- Oxidation-induced stress in a LOCOS structureIEEE Electron Device Letters, 1986
- A three-dimensional DRAM cell of stacked switching-transistor in SOI (SSS)Published by Institute of Electrical and Electronics Engineers (IEEE) ,1985
- Trench isolation prospects for application in CMOS VLSIPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1984
- An isolation-merged vertical capacitor cell for large capacity DRAMPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1984
- A corrugated capacitor cell (CCC) for megabit dynamic MOS memoriesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1982
- ST-CMOS (Stacked Transistors CMOS): A double-poly-NMOS-compatible CMOS technologyPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1981
- A general simulator for VLSI lithography and etching processes: Part II—Application to deposition and etchingIEEE Transactions on Electron Devices, 1980
- A String Model Etching AlgorithmPublished by Defense Technical Information Center (DTIC) ,1979
- A general simulator for VLSI lithography and etching processes: Part I—Application to projection lithographyIEEE Transactions on Electron Devices, 1979
- Line‐Profile resist development simulation techniquesPolymer Engineering & Science, 1977