Thermal performance and reliability aspects of silicon hybrid multi-chip modules

Abstract

Silicon hybrid thermal demonstrators which proved to be useful test vehicles with which to determine the thermal performance of silicon hybrids and their associated packaging have been built. The demonstrators are housed in custom packages having a high conductivity base, expansion-matched to the silicon substrate. Thermal performance has been determined for different methods of chip-to-substrate interconnection, and the reliability of bonds has been determined during power cycling. For wire-bonded chips, a thermal impedance of 1.7 kW-1 from chip surface to package base has been obtained using silver-filled adhesive-film die-attach material. Thermal impedances for area-bonded and peripherally bonded flip chips are 5.1 kW -1 and 7.0 kW-1, respectively. For silicon hybrids, it is power cycling of chips which limits flip-chip reliability rather than ambient temperature cycling. Reducing the thermal impedance between chip and ambient is the most effective route to increasing reliabilit