A subnanosecond integrated switching circuit with MESFET's for LSI
- 1 June 1976
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 11 (3), 385-394
- https://doi.org/10.1109/JSSC.1976.1050741
Abstract
Using a simple channel implantation step, the choice of the threshold voltage determines speed and power. Illustrations are given by the example of a 3-input NOR-gate with 1/spl times/5-/spl mu/m/SUP 2/ channel geometry for the switching transistors. A design with dual threshold voltages allowing the optimization of power consumption while keeping subnanosecond propagation delay times is presented and applied to a speed- and power-optimized dual-type MESFET NOR-gate. Examples are presented of experimental d.c. characteristics measured on fabricated samples exhibiting an average power consumption of 150 /spl mu/W. A propagation delay time of 0.8 ns is deduced for a fan-out of 3. This performance is discussed in conjunction with a set of parameters including geometry, technological reproducibility, and circuit design requirements. It appears that geometries of about 1 /spl mu/m lead to the best compromise for fast switching and optimized LSI organization.Keywords
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