Capless annealing of InP for metal-insulator-semiconductor field-effect transistor applications
- 1 September 1984
- journal article
- Published by AIP Publishing in Applied Physics Letters
- Vol. 45 (5), 532-534
- https://doi.org/10.1063/1.95304
Abstract
A simple capless annealing process for post-implantation annealing of InP material is described. The technique incorporates a simple boat design and uses InP+Sn as the source of phosphorus overpressure. Using this process, Si-implanted (4×1012 cm−2 dose) InP layers show mobilities at room temperature and 77 K in the range of 3200 and ∼10 000 cm2/Vs, respectively. Dopant depth profiles with peak donor densities of 2×1017 cm−3 and minimal redistribution of impurities were obtained. Depletion-mode InP metal-insulator-semiconductor field-effect transistors fabricated with 4-μm gate lengths using ion-implanted channel and source-drain regions, show channel mobilities of 2500 cm2/Vs.Keywords
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