Wide dynamic range four-quadrant CMOS analog multiplier using linearized transconductance stages
- 1 December 1986
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 21 (6), 1120-1122
- https://doi.org/10.1109/jssc.1986.1052656
Abstract
No abstract availableKeywords
This publication has 8 references indexed in Scilit:
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- A four-quadrant NMOS analog multiplierIEEE Journal of Solid-State Circuits, 1982
- A precise four-quadrant multiplier with subnanosecond responseIEEE Journal of Solid-State Circuits, 1968