Testing Logic Networks and Designing for Testability

1 October 1979

journal article
Published by Institute of Electrical and Electronics Engineers (IEEE) in Computer

Vol. 12 (10), 9-21
https://doi.org/10.1109/mc.1979.1658490

Abstract

VLSI has brought exciting increases in circuit density and performance capability. But it has also aggravated the problem of chip, component and system testing. Here are some approaches to dealing with that problem.

Keywords

This publication has 47 references indexed in Scilit:

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