A fault-tolerant 64K dynamic random-access memory
- 1 June 1979
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Electron Devices
- Vol. 26 (6), 853-860
- https://doi.org/10.1109/t-ed.1979.19509
Abstract
A 64K dynamic MOS RAM with features and performance fully compatible with current 16K RAM's has been designed and characterized. The memory cell is a one-transistor-one-capacitor structure, standard except for a polysilicon bit line. A dual-32K architecture, along with partial selection and stepped recovery, holds power and peak current values below those of 16K parts. Spare rows and columns, which can be substituted for defective elements by the laser opening of polysilicon links, enhance yield. Worst case column enable access time of the memory is 100 ns, row enable access time is 170 ns, and only 128 cycles within 4 ms are needed to refresh the device.Keywords
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