A ±5-V CMOS analog multiplier
- 1 December 1987
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 22 (6), 1143-1146
- https://doi.org/10.1109/jssc.1987.1052866
Abstract
No abstract availableKeywords
This publication has 4 references indexed in Scilit:
- Wide dynamic range four-quadrant CMOS analog multiplier using linearized transconductance stagesIEEE Journal of Solid-State Circuits, 1986
- A 20-V four-quadrant CMOS analog multiplierIEEE Journal of Solid-State Circuits, 1985
- A four-quadrant NMOS analog multiplierIEEE Journal of Solid-State Circuits, 1982
- A high-performance monolithic multiplier using active feedbackIEEE Journal of Solid-State Circuits, 1974