Two-dimensional effects in the bipolar polysilicon self-aligned transistor
- 1 November 1987
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Electron Devices
- Vol. 34 (11), 2297-2303
- https://doi.org/10.1109/t-ed.1987.23235
Abstract
There has been a great deal of interest recently in the performance enhancements afforded by self-aligned silicon transistors. Concomitantly, it has been observed that the current gain and collector drive capability of these devices sometimes exhibit a strong dependence an the geometrical size and shape of the emitter, In this study, it has been shown that this two-dimensional effect is explicable in terms of a parasitic p-n diode in parallel with the emitter-base junction. An accurate model has been developed to predict the geometry-dependent current gain under low to moderate bias. It is further shown how the model can be extended to the high-bias regime. Lastly, it is shown, by means of an emitter-base debiasing model, that the geometry of the emitter contact has a more significant effect on the emitter-base debiasing than does the intrinsic base sheet resistance itself.Keywords
This publication has 12 references indexed in Scilit:
- IVB-1 tunneling component in polysilicon self-aligned bipolar transistorsIEEE Transactions on Electron Devices, 1986
- A 30-ps Si bipolar IC using super self-aligned process technologyIEEE Transactions on Electron Devices, 1986
- Power dissipation calculation of the base spreading and contact resistance of transistors at low currents and low frequenciesIEEE Transactions on Electron Devices, 1986
- Emitter-Base Junction Size Effect on Current Gain Hfe of AlGaAs/GaAs Heterojunction Bipolar TransistorsJapanese Journal of Applied Physics, 1985
- A simple method for separation of the internal and external (peripheral) currents of bipolar transistorsSolid-State Electronics, 1984
- 1.25 /spl mu/m Deep-Groove-Isolated Self-Aligned Bipolar CircuitsIEEE Journal of Solid-State Circuits, 1982
- Electric measurement and modelling of the emitter base junction behaviour of VLSI silicon transistorSolid-State Electronics, 1981
- A two-lump transistor model for computer circuit simulationIEEE Journal of Solid-State Circuits, 1976
- Experimental model aid for planar design of transistor characteristics in integrated circuitsSolid-State Electronics, 1976
- Some Aspects of the Design of Power TransistorsProceedings of the IRE, 1955