Performance of CMOS differential circuits
- 1 June 1996
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 31 (6), 841-846
- https://doi.org/10.1109/4.509871
Abstract
No abstract availableThis publication has 9 references indexed in Scilit:
- Self-timed precharge latchPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Evaluation of two-summand adders implemented in ECDL CMOS differential logicIEEE Journal of Solid-State Circuits, 1991
- Implementation of iterative networks with CMOS differential logicIEEE Journal of Solid-State Circuits, 1988
- A comparison of CMOS circuit techniques: differential cascode voltage switch logic versus conventional logicIEEE Journal of Solid-State Circuits, 1987
- Design procedures for differential cascode voltage switch circuitsIEEE Journal of Solid-State Circuits, 1986
- Design-performance trade-offs in CMOS-domino logicIEEE Journal of Solid-State Circuits, 1986
- Differential split-level CMOS logic for subnanosecond speedsIEEE Journal of Solid-State Circuits, 1985
- Cascode voltage switch logic: A differential CMOS logic familyPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1984
- NORA: a racefree dynamic CMOS technique for pipelined logic structuresIEEE Journal of Solid-State Circuits, 1983